SIART Design Systems is a design services company with founders having more than 18 years of experience in ASIC Design Services and Embedded Software development. Our focus is to enable customers with IC Design, Embedded software, Software Testing and System Design Solutions, through a motivated team of skilled Engineers, who have the expertise in ASIC/SOC architecture design, RTL Coding and Verification, FPGA Design & Prototyping, Synthesis & STA, Formal Verification, DFT, PD, Analog Mixed Signal Design & Layout. Core Embedded Team has sound understanding of the embedded software.

We have Expertise from Pre-silicon development to boot loader to device drivers to hardware abstraction layers. Testing services Team supports enterprises effectively and ensure the products are tested adequately to meet the business and market expectations. SIART support customers in ensuring their products/applications meet quality standards.

SEMICONDUCTOR ENGINEERING SERVICES

You define!! We design!! Our strength at SIART is the ability to execute semiconductor projects.
SIART is focused on providing services and solutions in:

RTL Design Implementation:

Micro architecture Design and RTL Coding (Verilog,VHDL)
RTL top integration and verification
Low Power methodology (UPF)
AMBA AXI, AHB, APB Protocols, OCP, ARM Subsystems
Quality checks like LINT, CDC
Synthesis and Static Timing Analysis
Formal Verification, CLP, LEC

Design Verification:

IP and SOC level Verification Architecture development, Test Bench development
Low power architecture and CPF/UPF flow setup
System Verilog/Specman/UVM
Functional verification signoff (code coverage, functional coverage, formal verification, assertion, Gate-level simulation)
Power aware Gate level Simulation
Expert Design Verification

DFT Services:

DFT Planning, Architecture, Flow and Methodology Development.
DFT Implementation : UDR definitions for better controllability, Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression Logic Insertion, Boundary Scan Insertion, MBIST insertion and IOs.
ATPG, ATPG verification, ATE Patterns & Silicon debug
DFT simulations for zero delay and timing for SCAN, Boundary SCAN, MBIST & LBIST modes.
Pre-silicon and Post-silicon Debug.
ATE Test Program development and Production support.

Expert DFT | Physical Design and Verification:

Setting up Physical Design and Verification flow/methodology
Full chip and Block level Implementation from Advance Low Power methodology Implementation
High Speed design Implementation (ARM, GPU, DSP, WLAN IP subsystems).
Complex Block Implementation (Modem, Camera).
Full chip, Block level signoff closure (static timing analysis, formal verification, dynamic and leakage power, physical verification, low power).
Flow and methodology migration and support.
Technology experience on varying process nodes optimized for performance, power ranging from 28nm, 20nm, 16nm, 10nm and 7nm.

Expert Physical Design | Circuit and Layout Design

Analog, RF, PMIC, IO and Memory
SPEC to GDS for various Technology nodes
Foundation IP Design, Layout and Characterization : Standard cell, Memory and IO
Complete Library Development
Turnkey product Handover
7nm,28 nm & 32 nm are recent executions
Expert Circuit and Layout Design